Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM
نویسندگان
چکیده
منابع مشابه
DRAM-Aware Last-Level Cache Replacement
The cost of last-level cache misses and evictions depend significantly on three major performance-related characteristics of DRAM-based main memory systems: bank-level parallelism, row buffer locality, and write-caused interference. Bank-level parallelism and row buffer locality introduce different latency costs for the processor to service misses: parallel or serial, fast or slow. Write-caused...
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ژورنال
عنوان ژورنال: IEICE Transactions on Communications
سال: 2021
ISSN: 0916-8516,1745-1345
DOI: 10.1587/transcom.2020ebp3017